Copying SEPFW (0x750000 bytes)... Copying TrustCache (0x5c000 bytes)... Adjusting addresses in ADT... Setting up bootargs at 0x81db70000... Setting secondary CPU RVBARs... cpu1: [0x210150000] = 0x81ac50000 cpu2: [0x210250000] = 0x81ac50000 cpu3: [0x210350000] = 0x81ac50000 cpu4: [0x211050000] = 0x81ac50000 cpu5: [0x211150000] = 0x81ac50000 cpu6: [0x211250000] = 0x81ac50000 cpu7: [0x211350000] = 0x81ac50000 Disabling other iodevs... - IODEV.UART - IODEV.FB - IODEV.USB1 - IODEV.USB0_SEC - IODEV.USB1_SEC Doing essential MMIO remaps... Updating page tables... PT[200000000:235200000] -> HW PT[235200000:235204000] -> RESERVED VUART PT[235204000:23b7001c0] -> HW PT[23b7001c0:23b7001c4] -> RESERVED PMGR HACK PT[23b7001c4:23b700220] -> HW PT[23b700220:23b700224] -> RESERVED PMGR HACK PT[23b700224:23b700270] -> HW PT[23b700270:23b700274] -> RESERVED PMGR HACK PT[23b700274:23b700420] -> HW PT[23b700420:23b700424] -> RESERVED PMGR HACK PT[23b700424:23b700448] -> HW PT[23b700448:23b70044c] -> RESERVED PMGR HACK PT[23b70044c:23b754000] -> HW PT[23b754000:23b754010] -> RESERVED CPU_START PT[23b754010:23d280088] -> HW PT[23d280088:23d28008c] -> RESERVED PMGR HACK PT[23d28008c:23d280098] -> HW PT[23d280098:23d28009c] -> RESERVED PMGR HACK PT[23d28009c:23d29c044] -> HW PT[23d29c044:23d29c048] -> RESERVED PMGR HACK PT[23d29c048:23d29c05c] -> HW PT[23d29c05c:23d29c060] -> RESERVED PMGR HACK PT[23d29c060:700000000] -> HW Uploading ADT (0x53fa4 bytes)... Improving logo... Shutting down framebuffer... Enabling SPRR... Enabling GXF... Jumping to entrypoint at 0x81ac50800 [cpu0] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu0] Pass: mrs x0, HID5_EL1 = 2082df50e700df14 (HID5_EL1) [cpu0] Pass: msr HID5_EL1, x0 = 2082df50e700df14 (OK) (HID5_EL1) [cpu0] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1) [cpu0] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1) [cpu0] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1) [cpu0] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1) [cpu0] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu0] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu0] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu0] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu0] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu0] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu0] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu0] Skip: msr ACC_CFG_EL1, x1 = d CPUSTART W 23b754000+4:32 = 0x2 CPUSTART W 23b754000+8:32 = 0x2 [cpu0] Starting guest secondary 0:1 [cpu0] CPU #1: RVBAR = 0x81ac50000 TTY> HV: Initializing secondary 1 TTY> HV: Entering guest secondary 1 at 0x81ac50000 [cpu1] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu1] Pass: mrs x0, HID5_EL1 = 2082df50e700df14 (HID5_EL1) [cpu1] Pass: msr HID5_EL1, x0 = 2082df50e700df14 (OK) (HID5_EL1) [cpu1] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1) [cpu1] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1) [cpu1] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1) [cpu1] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1) [cpu1] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu1] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu1] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu1] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu1] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu1] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu1] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu1] Skip: msr ACC_CFG_EL1, x1 = d CPUSTART W 23b754000+4:32 = 0x4 CPUSTART W 23b754000+8:32 = 0x4 [cpu0] Starting guest secondary 0:2 [cpu0] CPU #2: RVBAR = 0x81ac50000 TTY> HV: Initializing secondary 2 TTY> HV: Entering guest secondary 2 at 0x81ac50000 [cpu2] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu2] Pass: mrs x0, HID5_EL1 = 2082df50e700df14 (HID5_EL1) [cpu2] Pass: msr HID5_EL1, x0 = 2082df50e700df14 (OK) (HID5_EL1) [cpu2] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1) [cpu2] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1) [cpu2] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1) [cpu2] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1) [cpu2] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu2] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu2] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu2] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu2] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu2] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu2] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu2] Skip: msr ACC_CFG_EL1, x1 = d CPUSTART W 23b754000+4:32 = 0x8 CPUSTART W 23b754000+8:32 = 0x8 [cpu0] Starting guest secondary 0:3 [cpu0] CPU #3: RVBAR = 0x81ac50000 TTY> HV: Initializing secondary 3 TTY> HV: Entering guest secondary 3 at 0x81ac50000 [cpu3] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu3] Pass: mrs x0, HID5_EL1 = 2082df50e700df14 (HID5_EL1) [cpu3] Pass: msr HID5_EL1, x0 = 2082df50e700df14 (OK) (HID5_EL1) [cpu3] Pass: mrs x0, EHID9_EL1 = 600000811 (EHID9_EL1) [cpu3] Pass: msr EHID9_EL1, x0 = 600000811 (OK) (EHID9_EL1) [cpu3] Pass: mrs x0, EHID10_EL1 = 3000528002788 (EHID10_EL1) [cpu3] Pass: msr EHID10_EL1, x0 = 3000528002788 (OK) (EHID10_EL1) [cpu3] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu3] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu3] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu3] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu3] Pass: mrs x0, EHID20_EL1 = 618100 (EHID20_EL1) [cpu3] Pass: msr EHID20_EL1, x0 = 618100 (OK) (EHID20_EL1) [cpu3] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu3] Skip: msr ACC_CFG_EL1, x1 = d CPUSTART W 23b754000+4:32 = 0x10 CPUSTART W 23b754000+c:32 = 0x1 [cpu0] Starting guest secondary 1:0 [cpu0] CPU #4: RVBAR = 0x81ac50000 TTY> HV: Initializing secondary 4 TTY> HV: Entering guest secondary 4 at 0x81ac50000 [cpu4] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu4] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu4] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu4] Pass: mrs x0, HID1_EL1 = 40000002000000 (HID1_EL1) [cpu4] Pass: msr HID1_EL1, x0 = 40000002000000 (OK) (HID1_EL1) [cpu4] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu4] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu4] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu4] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu4] Pass: mrs x0, HID6_EL1 = 7dc8031f007c0e (HID6_EL1) [cpu4] Pass: msr HID6_EL1, x0 = 7dc8031f007c0e (OK) (HID6_EL1) [cpu4] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu4] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu4] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu4] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu4] Pass: mrs x0, HID9_EL1 = 100086c000000 (HID9_EL1) [cpu4] Pass: msr HID9_EL1, x0 = 100086c000000 (OK) (HID9_EL1) [cpu4] Pass: mrs x0, HID11_EL1 = 804000010000000 (HID11_EL1) [cpu4] Pass: msr HID11_EL1, x0 = 804000010000000 (OK) (HID11_EL1) [cpu4] Pass: mrs x0, HID13_EL1 = 332200211010205 (HID13_EL1) [cpu4] Pass: msr HID13_EL1, x0 = 332200211010205 (OK) (HID13_EL1) [cpu4] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu4] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu4] Pass: mrs x0, HID18_EL1 = 40004000 (HID18_EL1) [cpu4] Pass: msr HID18_EL1, x0 = 40004000 (OK) (HID18_EL1) [cpu4] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu4] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu4] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu4] Skip: msr ACC_CFG_EL1, x1 = d CPUSTART W 23b754000+4:32 = 0x20 CPUSTART W 23b754000+c:32 = 0x2 [cpu0] Starting guest secondary 1:1 [cpu0] CPU #5: RVBAR = 0x81ac50000 TTY> HV: Initializing secondary 5 TTY> HV: Entering guest secondary 5 at 0x81ac50000 [cpu5] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu5] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu5] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu5] Pass: mrs x0, HID1_EL1 = 40000002000000 (HID1_EL1) [cpu5] Pass: msr HID1_EL1, x0 = 40000002000000 (OK) (HID1_EL1) [cpu5] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu5] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu5] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu5] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu5] Pass: mrs x0, HID6_EL1 = 7dc8031f007c0e (HID6_EL1) [cpu5] Pass: msr HID6_EL1, x0 = 7dc8031f007c0e (OK) (HID6_EL1) [cpu5] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu5] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu5] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu5] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu5] Pass: mrs x0, HID9_EL1 = 100086c000000 (HID9_EL1) [cpu5] Pass: msr HID9_EL1, x0 = 100086c000000 (OK) (HID9_EL1) [cpu5] Pass: mrs x0, HID11_EL1 = 804000010000000 (HID11_EL1) [cpu5] Pass: msr HID11_EL1, x0 = 804000010000000 (OK) (HID11_EL1) [cpu5] Pass: mrs x0, HID13_EL1 = 332200211010205 (HID13_EL1) [cpu5] Pass: msr HID13_EL1, x0 = 332200211010205 (OK) (HID13_EL1) [cpu5] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu5] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu5] Pass: mrs x0, HID18_EL1 = 40004000 (HID18_EL1) [cpu5] Pass: msr HID18_EL1, x0 = 40004000 (OK) (HID18_EL1) [cpu5] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu5] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu5] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu5] Skip: msr ACC_CFG_EL1, x1 = d CPUSTART W 23b754000+4:32 = 0x40 CPUSTART W 23b754000+c:32 = 0x4 [cpu0] Starting guest secondary 1:2 [cpu0] CPU #6: RVBAR = 0x81ac50000 TTY> HV: Initializing secondary 6 TTY> HV: Entering guest secondary 6 at 0x81ac50000 [cpu6] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu6] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu6] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu6] Pass: mrs x0, HID1_EL1 = 40000002000000 (HID1_EL1) [cpu6] Pass: msr HID1_EL1, x0 = 40000002000000 (OK) (HID1_EL1) [cpu6] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu6] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu6] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu6] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu6] Pass: mrs x0, HID6_EL1 = 7dc8031f007c0e (HID6_EL1) [cpu6] Pass: msr HID6_EL1, x0 = 7dc8031f007c0e (OK) (HID6_EL1) [cpu6] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu6] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu6] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu6] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu6] Pass: mrs x0, HID9_EL1 = 100086c000000 (HID9_EL1) [cpu6] Pass: msr HID9_EL1, x0 = 100086c000000 (OK) (HID9_EL1) [cpu6] Pass: mrs x0, HID11_EL1 = 804000010000000 (HID11_EL1) [cpu6] Pass: msr HID11_EL1, x0 = 804000010000000 (OK) (HID11_EL1) [cpu6] Pass: mrs x0, HID13_EL1 = 332200211010205 (HID13_EL1) [cpu6] Pass: msr HID13_EL1, x0 = 332200211010205 (OK) (HID13_EL1) [cpu6] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu6] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu6] Pass: mrs x0, HID18_EL1 = 40004000 (HID18_EL1) [cpu6] Pass: msr HID18_EL1, x0 = 40004000 (OK) (HID18_EL1) [cpu6] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu6] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu6] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu6] Skip: msr ACC_CFG_EL1, x1 = d CPUSTART W 23b754000+4:32 = 0x80 CPUSTART W 23b754000+c:32 = 0x8 [cpu0] Starting guest secondary 1:3 [cpu0] CPU #7: RVBAR = 0x81ac50000 TTY> HV: Initializing secondary 7 TTY> HV: Entering guest secondary 7 at 0x81ac50000 [cpu7] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1) [cpu7] Pass: mrs x0, HID0_EL1 = 10002990120e0e00 (HID0_EL1) [cpu7] Pass: msr HID0_EL1, x0 = 10002990120e0e00 (OK) (HID0_EL1) [cpu7] Pass: mrs x0, HID1_EL1 = 40000002000000 (HID1_EL1) [cpu7] Pass: msr HID1_EL1, x0 = 40000002000000 (OK) (HID1_EL1) [cpu7] Pass: mrs x0, HID3_EL1 = 4180000cf8001fe0 (HID3_EL1) [cpu7] Pass: msr HID3_EL1, x0 = 4180000cf8001fe0 (OK) (HID3_EL1) [cpu7] Pass: mrs x0, HID5_EL1 = 2082df205700ff12 (HID5_EL1) [cpu7] Pass: msr HID5_EL1, x0 = 2082df205700ff12 (OK) (HID5_EL1) [cpu7] Pass: mrs x0, HID6_EL1 = 7dc8031f007c0e (HID6_EL1) [cpu7] Pass: msr HID6_EL1, x0 = 7dc8031f007c0e (OK) (HID6_EL1) [cpu7] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu7] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu7] Pass: mrs x0, HID7_EL1 = 3110000 (HID7_EL1) [cpu7] Pass: msr HID7_EL1, x0 = 3110000 (OK) (HID7_EL1) [cpu7] Pass: mrs x0, HID9_EL1 = 100086c000000 (HID9_EL1) [cpu7] Pass: msr HID9_EL1, x0 = 100086c000000 (OK) (HID9_EL1) [cpu7] Pass: mrs x0, HID11_EL1 = 804000010000000 (HID11_EL1) [cpu7] Pass: msr HID11_EL1, x0 = 804000010000000 (OK) (HID11_EL1) [cpu7] Pass: mrs x0, HID13_EL1 = 332200211010205 (HID13_EL1) [cpu7] Pass: msr HID13_EL1, x0 = 332200211010205 (OK) (HID13_EL1) [cpu7] Pass: mrs x0, HID16_EL1 = 6900000440000000 (HID16_EL1) [cpu7] Pass: msr HID16_EL1, x0 = 6900000440000000 (OK) (HID16_EL1) [cpu7] Pass: mrs x0, HID18_EL1 = 40004000 (HID18_EL1) [cpu7] Pass: msr HID18_EL1, x0 = 40004000 (OK) (HID18_EL1) [cpu7] Pass: mrs x0, HID21_EL1 = 1040000 (HID21_EL1) [cpu7] Pass: msr HID21_EL1, x0 = 1040000 (OK) (HID21_EL1) [cpu7] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1) [cpu7] Skip: msr ACC_CFG_EL1, x1 = d [cpu0] PMGR R 23b7001c0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR W 23b7001c0+0:32 = 0xf0000ff: Dangerous write [cpu0] PMGR R 23b7001c0+0:32 = 0xf0000ff -> 0xf0000ff [cpu0] PMGR R 23b700448+0:32 = 0x23ff -> 0x23ff [cpu0] PMGR W 23b700448+0:32 = 0x23ff: Dangerous write [cpu0] PMGR R 23b700448+0:32 = 0x20ff -> 0x20ff [cpu0] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1) [cpu1] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1) [cpu2] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1) [cpu3] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1) [cpu4] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1) [cpu5] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1) [cpu6] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1) [cpu7] Pass: msr MDSCR_EL1, x1 = 1000 (OK) (MDSCR_EL1) [cpu0] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu0] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu1] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu1] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu2] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu2] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu3] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu3] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu4] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu4] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu5] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu5] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu6] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu6] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu7] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1) [cpu7] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1) [cpu0] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1) [cpu0] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1) [cpu0] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5) [cpu0] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4) [cpu0] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5) [cpu0] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4) [cpu0] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5) [cpu0] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4) [cpu0] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5) [cpu0] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4) [cpu0] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu0] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu0] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1) [cpu0] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1) [cpu0] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7) [cpu0] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6) [cpu0] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7) [cpu0] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6) [cpu0] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7) [cpu0] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6) [cpu1] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1) [cpu1] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1) [cpu1] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5) [cpu1] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4) [cpu1] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5) [cpu1] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4) [cpu1] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5) [cpu1] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4) [cpu1] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5) [cpu1] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4) [cpu1] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu1] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu1] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1) [cpu1] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1) [cpu1] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7) [cpu1] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6) [cpu1] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7) [cpu1] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6) [cpu1] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7) [cpu1] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6) [cpu2] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1) [cpu2] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1) [cpu2] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5) [cpu2] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4) [cpu2] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5) [cpu2] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4) [cpu2] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5) [cpu2] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4) [cpu2] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5) [cpu2] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4) [cpu2] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu2] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu2] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1) [cpu2] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1) [cpu2] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7) [cpu2] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6) [cpu2] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7) [cpu2] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6) [cpu2] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7) [cpu2] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6) [cpu3] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1) [cpu3] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1) [cpu3] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5) [cpu3] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4) [cpu3] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5) [cpu3] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4) [cpu3] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5) [cpu3] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4) [cpu3] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5) [cpu3] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4) [cpu3] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu3] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu3] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1) [cpu3] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1) [cpu3] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7) [cpu3] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6) [cpu3] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7) [cpu3] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6) [cpu3] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7) [cpu3] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6) [cpu4] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1) [cpu4] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1) [cpu4] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5) [cpu4] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4) [cpu4] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5) [cpu4] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4) [cpu4] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5) [cpu4] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4) [cpu4] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5) [cpu4] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4) [cpu4] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu4] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu4] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1) [cpu4] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1) [cpu4] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7) [cpu4] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6) [cpu4] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7) [cpu4] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6) [cpu4] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7) [cpu4] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6) [cpu5] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1) [cpu5] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1) [cpu5] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5) [cpu5] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4) [cpu5] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5) [cpu5] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4) [cpu5] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5) [cpu5] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4) [cpu5] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5) [cpu5] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4) [cpu5] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu5] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu5] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1) [cpu5] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1) [cpu5] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7) [cpu5] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6) [cpu5] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7) [cpu5] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6) [cpu5] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7) [cpu5] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6) [cpu6] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1) [cpu6] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1) [cpu6] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5) [cpu6] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4) [cpu6] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5) [cpu6] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4) [cpu6] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5) [cpu6] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4) [cpu6] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5) [cpu6] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4) [cpu6] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu6] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu6] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1) [cpu6] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1) [cpu6] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7) [cpu6] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6) [cpu6] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7) [cpu6] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6) [cpu6] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7) [cpu6] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6) [cpu7] Pass: msr DBGBCR15_EL1, x2 = 0 (OK) (DBGBCR15_EL1) [cpu7] Pass: msr DBGBVR15_EL1, x2 = 0 (OK) (DBGBVR15_EL1) [cpu7] Pass: msr s2_0_c0_c1_5, x2 = 0 (OK) (s2_0_c0_c1_5) [cpu7] Pass: msr s2_0_c0_c1_4, x2 = 0 (OK) (s2_0_c0_c1_4) [cpu7] Pass: msr s2_0_c0_c2_5, x2 = 0 (OK) (s2_0_c0_c2_5) [cpu7] Pass: msr s2_0_c0_c2_4, x2 = 0 (OK) (s2_0_c0_c2_4) [cpu7] Pass: msr s2_0_c0_c3_5, x2 = 0 (OK) (s2_0_c0_c3_5) [cpu7] Pass: msr s2_0_c0_c3_4, x2 = 0 (OK) (s2_0_c0_c3_4) [cpu7] Pass: msr s2_0_c0_c4_5, x2 = 0 (OK) (s2_0_c0_c4_5) [cpu7] Pass: msr s2_0_c0_c4_4, x2 = 0 (OK) (s2_0_c0_c4_4) [cpu7] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5) [cpu7] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4) [cpu7] Pass: msr DBGWCR15_EL1, x2 = 0 (OK) (DBGWCR15_EL1) [cpu7] Pass: msr DBGWVR15_EL1, x2 = 0 (OK) (DBGWVR15_EL1) [cpu7] Pass: msr s2_0_c0_c1_7, x2 = 0 (OK) (s2_0_c0_c1_7) [cpu7] Pass: msr s2_0_c0_c1_6, x2 = 0 (OK) (s2_0_c0_c1_6) [cpu7] Pass: msr s2_0_c0_c2_7, x2 = 0 (OK) (s2_0_c0_c2_7) [cpu7] Pass: msr s2_0_c0_c2_6, x2 = 0 (OK) (s2_0_c0_c2_6) [cpu7] Pass: msr s2_0_c0_c3_7, x2 = 0 (OK) (s2_0_c0_c3_7) [cpu7] Pass: msr s2_0_c0_c3_6, x2 = 0 (OK) (s2_0_c0_c3_6)